1. Technical Field
The present invention relates to memory systems, and, more particularly, to methods, systems and devices for estimating temporal degradation in memory systems.
2. Description of the Related Art
Memory elements of circuits, such as VLSI (Very Large Scale Integration) circuits, are designed using imperfect processes. As such, numerous tests are typically run to assess the functionality of the memory elements and to determine their yield based on the assessments. In particular, temporal degradation of the memory elements is estimated to determine the yield. However, models that over-estimate the temporal degradation can lead to the discarding of dies that actually meet system specifications. In turn, models that under-estimate the temporal degradation can lead to the release of packaged integrated circuits that may degrade at a customer's location. As such, accurate estimations of temporal degradations should be used to maximize yield.